銆�銆�楂橀�歋DM660騫沖彴鎵撻�犵殑瀹夊崜鏍稿績鏉匡紝閲囩敤鍏堣繘鐨?4綰崇背宸ヨ壓鍒剁▼錛屾惌杞藉叓鏍稿鐞嗗櫒鏋舵瀯錛屽寘鍚?棰桝73鏍稿績涓婚涓?.2GHz錛岃緟浠?棰桝53鏍稿績涓婚1.8GHz錛屾牳蹇冩澘灝哄涓?1.5脳45.5脳3.0姣背錛屽皝瑁呭艦寮忛噰鐢↙CC+LGA錛屽吋欏炬�ц兘涓庝綋縐�?/p>
銆�銆�榪欐鏍稿績鏉垮唴緗瓵dreno 512
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9鎿嶄綔緋葷粺銆傚瓨鍌ㄩ厤緗鏍鳳紝鎻愪緵3GB RAM+32GB瀛樺偍銆?GB RAM+64GB瀛樺偍鍜?GB RAM+128GB瀛樺偍絳夊縐嶇粍鍚堥�夐」銆傜綉緇滄�ц兘寮哄ぇ錛屾敮鎸丩TE
Cat.6錛屾渶澶т笅琛岄�熺巼杈懼埌300Mbps錛屼笂琛岄�熺巼鍙揪50Mbps錛屽吋瀹瑰縐嶉�氫俊鍒跺紡錛屽寘鎷琓D-LTE銆丗DD-LTE銆乄CDMA銆丒VDO銆乀D-SCDMA銆丆DMA鍙奊SM錛屽唴緗瓽NSS瀹氫綅銆佸弻棰?.4GHz/5GHz
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銆�銆�楂橀�歋DM660鏍稿績鏉垮弬鏁?/strong>
銆�銆�CPU錛歋DM660, 4脳A73 2.2GHz & 4脳A53 1.8GHz
銆�銆�GPU錛欰dreno 512
銆�銆�鎿嶄綔緋葷粺錛欰ndroid 9
銆�銆�瀛樺偍錛?GB LPDDR4x + 32GB eMMC(Option 4G/6G+64G/128G)
銆�銆�LCM鎺ュ彛錛?-lane MIPI_DSI0 + 4-lane MIPI_DSI1 2560*1600 @60fps
銆�銆�DP錛?K@30fps, 2K@60fps
銆�銆�鏀寔鍙屽睆寮傛樉
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銆�銆�瑙嗛瑙ｇ爜錛?K @ 30 fps; H.264/VP8/VP9/HEVC
銆�銆�瑙嗛緙栫爜錛?K @ 30 fps; HEVC/H264/VP8/MPEG-4
銆�銆�緗戠粶鍒跺紡錛歍D-LTE/FDD-LTE/WCDMA/EVDO/TD-SCDMA/CDMA/GSM
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銆�銆�宸ヤ綔鐢靛帇錛?.5V~4.35V(鍏稿瀷鍊鹼細3.8V)
銆�銆�灝佽鐗規�э細 LCC+LGA
銆�銆�澶栧艦灝哄錛?41.5脳45.5脳3mm